with central arbiters for serializing bus access requests. This simple solution has serious scalability properties, leading to critical performance penalties and energy inefficiencies as the number of integrated cores increases. There is a world-wide ongoing effort to design more scalable communication architectures, for instance leveraging network technology and adapting it to the on-chip scenario. The resulting architectures are known as “Networks-on-Chip” (NoCs) and have some promising features for application to giga-scale systems-on-chip such as high modularity, scalability, potentials or energy savings (e.g., application-specific NoCs) despite the increased design complexity.